1. Field of the Invention
The present invention relates to a method for manufacturing non-volatile memory devices integrated on a semiconductor substrate.
More specifically the invention relates to a method for manufacturing non-volatile memory devices integrated on a semiconductor substrate and comprising a matrix of memory cells and an associated circuitry, the method comprising the following steps:                forming a plurality of gate electrodes of said memory cells projecting from said semiconductor substrate in said matrix, said plurality of gate electrodes comprising a plurality of conductive layers;        forming at least one conductive layer in said circuitry;        forming conductive regions of said memory cells in said semiconductor substrate.        
The invention particularly, but not exclusively, relates to a method for making some steps of the manufacturing processes of electronic devices containing non-volatile memory cells of the floating gate type with NOR architecture independent from each other and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, non-volatile memory electronic devices, for example of the EPROM and Flash EEPROM type with NOR architecture, integrated on semiconductor comprise a plurality of matrix-like organised non-volatile memory cells; i.e. the cells are organised in rows, called word lines, and columns, called bit lines.
Each single non-volatile memory cell comprises a MOS transistor wherein the gate electrode, placed above the channel region, is floating, i.e. it has a high impedance in DC towards all the other terminals of the same cell and of the circuit wherein the cell is inserted. Generally, the gate electrode is formed by means of a polysilicon layer.
The cell also comprises a second electrode, called control gate, which is capacitively coupled to the floating gate electrode through an intermediate dielectric layer, so called interpoly. Generally, the control electrode is formed by means of a polysilicon layer. This second electrode is driven through suitable control voltages. The other terminals of the transistor are the usual drain and source regions.
Inside the matrix of the memory cell, cells belonging to a same word line share the electric line which drives the respective control gates, while the cells belonging to a same bit line share the drain regions.
By applying suitable voltage values to the cell terminals, it is possible to vary the amount of charge present in the floating gate, for example by using the known Channel Hot Electrons Injection phenomena, carrying out the programming.
The matrix of memory cells is associated with a control circuit comprising a plurality of MOS transistors, each comprising a source region and a drain region separated from a channel region. A gate electrode is then formed on the channel region and insulated from this by means of a gate oxide layer. Moreover, insulating spacers are provided on the side walls of the gate electrode.
In particular, in the circuitry of new generation memory matrixes of the Flash type with NOR architecture also MOS transistors and having high performances are integrated in the circuitry for embedded applications and for carrying out, at high speed, the complex management algorithms of the memory devices themselves.
To form, inside the circuitry, both these advanced technology transistors and transistors managing the high voltages necessary to ensure the functionality of the memory cell in reading, process steps are used for the formation of the junction implants forming the source and drain regions and the spacers which are particularly complex. There is in fact the need to introduce differentiated spacers and junction implants, in correspondence with the different typologies of transistors to be formed.
Moreover, these process steps for the formation of the spacers are not necessary for the formation of the NOR memory cells which are programmed for channel hot electrons and whose operation instead requires specific junctions self-aligned to the floating gate.
Moreover, the sizes and the conductive materials of the spacers of the circuitry transistors can become a strict constraint for the scalability of the memory cell, in particular for the possible silicidisation process of the drain regions, for the pre-metal filling process, for the integration of the drain contacts and for the sustainability of the reading disturbances.
Moreover the formation of the pre-metal filling layer in the matrix is tied to the maximum thermal budget sustainable by the circuitry transistors and by the silicide layer if any.